The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
As merely one example, in some applications, overall performance of an IC may be improved by tailoring the constituent circuit elements to their particular roles. For example, circuit elements may be tuned by varying the composition of the gate stack. However, as the number of differentiated circuit elements in a single IC grows, the complexity of manufacturing the IC may also increase as a result. With each additional step in the manufacturing process, the yield risk increases. Compounding the difficulty, many advanced materials, including high-k dielectrics and metal gates in the gate stack example, are sensitive and may be damaged by conventional processes for producing layers of varying composition. Therefore, although existing semiconductor fabrication process have been generally adequate, they have not proved entirely satisfactory in all respects.